Field of the Invention
The present invention relates generally to the use of a non-volatile storage device, such as an electrically erasable programmable read only memory device (“EEPROM”), to store information regarding the location of failed parts on a multi-chip module such as a memory module. More particularly, the present invention relates to storing, in an on-module EEPROM, the identities of module output terminals, such as data query (“DQ”) terminals which, during testing of the module, have been determined to fail and are thus indicative of the locations of corresponding failed components.
State of the Art
Recent computer memory modules include a non-volatile storage device, such as an electrically erasable programmable read only memory device (“EEPROM”), an erasable programmable read only memory device (“EPROM”), a ferro-electronic device or a flash memory chip, on the memory module with other volatile storage devices such as random access memory (“RAM”), synchronous dynamic random access memory (“SDRAM”) and dynamic random access memory (“DRAM”). Volatile storage devices are those memory devices in which information stored in a memory cell in the device is completely lost when the power supply voltage applied to the memory cell is interrupted or turned off. In contrast, information stored in the cells of non-volatile storage devices is preserved when the power supply is turned off. A non-volatile storage device on a memory module is conventionally used to store valuable configuration information necessary for the processor to access the memory on the module. The configuration information stored on the non-volatile storage device includes such parameters as the latency and speed of the module components and the size and type of memory module, and is accessed by the processor during initialization of the system. The memory of the EEPROM is divided into sections, each section storing a different category of information.
Typically, however, the capacity of the EEPROM, or other long-term memory storage device, is greater than the memory requirements for the configuration information that needs to be stored. The industry has established a standard of a minimum of 128 bytes as the volume of configuration data to be stored on the non-volatile storage device. Therefore, any EEPROM memory (in excess of 128 bytes) remaining unused may be used to store additional information that is not material to the functionality of the module. The memory capacity of an EEPROM in excess of 128 bytes varies by the capacity of the EEPROM used.
U.S. Pat. No. 5,996,096 to Dell et al. (Nov. 30, 1999), the disclosure of which is hereby incorporated herein by reference, discloses using the excess memory capacity of an EPROM mounted on a memory module to store a map of the bad memory addresses of “reduced specification DRAM chips” (e.g., chips with nonfunctional memory addresses or partially defective DRAM chips) for use during operation of the memory module. According to the invention of Dell et al., each of a plurality of memory chips or dice is coded and marked with a unique identifier and tested in accordance with conventional testing methods. FIGS. 1-3 depict an example of the invention of Dell et al. using a 72 pin single in-line memory module (“SIMM”) 2 comprising a printed circuit board (“PCB”) 4 having a plurality of electrical contacts 6 (72 in the illustrated example) along one edge. Those tested memory chips having one or more bad memory cells are identified as “reduced specification chips” 8, 10, 12, 14, 16, 18, 20 and 22 and are placed together on the SIMM 2. The reduced specification chips are identified and their positions recorded using their respective unique identifiers (not shown). The address maps which identify specific bad addresses for each of the chips 8, 10, 12, 14, 16, 18, 20 and 22 are programmed into an EPROM 24 placed on the PCB 4 and associated with each of the respective unique identifiers of the chips 8, 10, 12, 14, 16, 18, 20 and 22. During later testing or operation of the memory module, the address map stored in the EPROM 24 is routinely accessed and updated by system processes to enable a logic device 26, such as an application-specific integrated circuit (“ASIC”) or other programmable logic device that contains the bit steering logic and timing generation logic, to redirect the data for defective DRAM addresses to an alternate storage device for all read and write operations in real time.
Memory Corporation of the United Kingdom sells a dual-in-line memory module built with a number of partially defective SDRAM dice. The synchronous dynamic random access memory dice (“SDRAM”) used on the dual in-line memory module (“DIMM”) are selected to ensure that the total number of defects is within the mapping capabilities of the ASIC. A map of the defective locations is stored in a serial EEPROM mounted on the DIMM. The mapping data is loaded into the ASIC at power-up together with the configuration information to redirect the data for defective DRAM addresses to an alternate storage device.
U.S. Pat. No. 5,963,463 to Rondeau, II et al. (Oct. 5, 1999), the disclosure of which is hereby incorporated herein by reference, also discloses an example of a memory module and method employing an EEPROM. According to the method of Rondeau, II et al., an EEPROM is programmed with module information after completion of the memory module assembly.
Memory chip manufactures conventionally employ chip-testing systems to individually test each memory chip. These systems test the operability of each memory chip by writing a value into each memory cell within the chip and then reading the contents of that cell. An example of an individual chip testing system is described in U.S. Pat. No. 5,991,215 to Brunelle (Nov. 23, 1999), the disclosure of which is hereby incorporated herein by reference.
The DRAM dice of memory modules are tested subsequent to connection to the memory module's printed circuit board (“PCB”) in addition to testing the individual DRAM dice prior to connection because failures may be caused by connection of the dice to the PCB or by the combination of the particular module components. After module testing, the memory modules are reworked, repaired, scrapped, stripped, repinned, rebuilt onto a module, depopulated or “depopped” (memory chips are removed from a module to re-run through chip testing) or sold as a depop product as is well known to one of ordinary skill in the art. Presently, memory modules are tested one module at a time in a wide range of tests to evaluate such things as speed, margin, voltage ranges, output and input levels, data patterns, functionality and connectivity of printed circuits, as well as being performance tested by operation in personal computers produced by various manufacturers, etc. To identify which specific DRAMs on a module fail one or more in a series of memory tests, the operator must either closely watch the tester monitor and record the location of a failing DRAM on a display map while the tester is testing the next module, or retest a module identified as having a failed DRAM. Because performance requirements for memory modules are constantly increasing, module testing processes are likewise becoming more complex and, consequently, longer and more expensive. Understandably, the cost of equipment to perform these more complex tests is also increasing. Present module testers may cost anywhere from $1.2-3 million each. Including module handlers, a module tester system may cost anywhere from $1.7-3.5 million.
To help reduce overall cost in these more expensive testers, module tester designers have added the ability to test multiple memory modules in parallel rather than one at a time. Examples of such memory module testers are manufactured by Advantest America of Santa Clara, Calif., and Teradyne of Boston, Mass. Module testers that can test up to 16 modules at a time are presently in development, though this number and the cost of equipment for testing modules will certainly continue to increase as performance requirements increase.
To illustrate how the testing process may affect the cost of a memory module, consider the following example. A process which could test 16 memory modules in parallel through a five-minute test would produce 192 modules per hour. Assuming a 25% failure rate, which is not atypical, there would be 48 of the 192 memory modules tested that fail the test process. However, when testing 16 modules at a time in parallel, identifying and marking failures by watching a test monitor during testing is no longer feasible. The modules identified as failed are therefore retested, one at a time, to identify which parts failed for each module. Due to parallelism, the time it takes to test one module or 16 modules is the same (5 minutes). Therefore, it would take a minimum of 4 hours (48 modules×5 min./module) to find the defects on the 48 failing modules.
The depreciation cost alone on a $1.7 million module tester system is roughly $39 per hour. Thus, the initial module test cost resulting from the equipment alone is $0.20 per module. Contrarily, the cost to retest the 48 failures discovered during the initial test is $3.25 per module, a significant increase over the initial test cost. This results in an average module testing cost before rework of $1.02 per module, five times more expensive than without the retesting. It is thus desirable to have a method of testing memory modules that avoids the costly retesting of the memory modules.